The present invention relates generally to design tools for integrated circuits. More specifically, but without limitation thereto, the present invention relates to a method for placing clock buffers within a partition of an integrated circuit to minimize clock skew.
Integrated circuits typically include blocks or partitions of multiple circuit elements such as flip-flops, cores, and building block circuits referred to by the equivalent names megacells, hard macros, and xe2x80x9chardmacsxe2x80x9d. The circuit elements are generally synchronized by a common clock signal from a clock buffer located within each partition. Using current methods for balanced clock placement, the number of clock buffers driven by repeaters is minimized, while downstream delays of each buffer are ignored. Also, ignoring the location of megacells produces groups of circuit elements with large insertion delays. The inability to estimate maximum and minimum delays in groups of circuit elements results in unbalanced partitioning with large clock skew and insertion delay. The unbalanced partitioning requires delay balancing by extra wire insertion, resulting in large errors in delay calculations. A circuit may be partitioned in a single iteration, called one-pass partitioning, or the circuit may be partitioned by an algorithm that examines all cells in several iterations. A partition of a circuit into two parts is called two-way cutting. Two-way cutting may be repeated to further partition a circuit. One-pass partitioning based on two-way cutting does not generally produce good solutions to the problem of balanced clock placement in production designs.
Further, heuristic objective functions used to place clock buffers in groups of circuit elements result in a large clock skew. Heuristic objective functions are quality functions that describe an objective or goal indirectly. An example of a heuristic objective function used to place clock buffers in groups of circuit elements is the minimization of the distance between a buffer location and the center of mass of a group of cells driven by the buffer. The real objective is the minimization of clock skew between the buffer and each cell in the group.
The present invention advantageously addresses the problems above as well as other problems by providing a balanced clock placement method that minimizes clock skew.
In one embodiment, the present invention may be characterized as a method of clock buffer placement for minimizing clock skew that includes the steps of (a) constructing a trunk delay model for a plurality of clock cells within a partitioning group, (b) placing a clock buffer at an initial location in the trunk delay model, (c) estimating a clock skew and an insertion delay from the trunk delay model, (d) checking whether the clock skew exceeds a clock skew limit, and (e) if the clock skew exceeds the clock skew limit, then selecting a new location for the clock buffer in the trunk delay model.